This invention relates generally to the physical layout of semiconductor systems. More particularly, this invention relates to a high density planar semiconductor system with a controlled impedance co-planar interconnect channel.
Semiconductor systems are implemented in a variety of configurations. One type of semiconductor system is a master-slave system in which a semiconductor-based master device controls a set of semiconductor-based slave devices. An example of a master-slave system is a memory system in which a master device memory controller coordinates the operation of a set of slave devices in the form of memory modules. By way of example, the invention is described in the context of a memory system, although the invention is equally applicable to other types of semiconductor systems.
As computer processors increase in speed, there is a growing burden being placed upon memory systems that provide data to computer processors. For example, video and three-dimensional image processing places a large burden on a computer memory subsystem.
One or more high frequency buses are typically employed to provide the required bandwidth in such systems. The higher the frequency of operation of the bus, the greater the requirement that the signals on the bus have high-fidelity and equal propagation times to the devices making up the subsystem. High-fidelity signals are signals having little or no ringing, and which have controlled and steady rising and falling edge rates.
Many obstacles are encountered in assuring the uniform arrival times of high-fidelity signals to devices on the bus. One issue is whether the bus is routed in a straight line or routed with turns. Turns of the lines may not permit the construction of the bus lines in a way necessary to achieve uniform arrival times of high-fidelity signals to devices on the bus.
The assignee of the present invention has filed a patent application entitled xe2x80x9cHigh Frequency Bus Systemxe2x80x9d, Ser. No. 08/938,084, filed Sep. 26, 1997, the contents of which are expressly incorporated herein. The foregoing patent application discloses a digital system 20 of the type shown in FIG. 1. The system 20 includes a mother board 22, which supports a master device 24 and a set of slave modules 26A, 26B, and 26C. A bus 28 is routed in a horizontal and vertical manner to interconnect the master device 24 with the set of slave modules 26A, 26B, and 26C, as shown in FIG. 1. The bus 28 is terminated in a resistor 30.
FIG. 2 is a side view of one of the modules 26 of FIG. 1. Module 26 has a set of slave devices 32A-32E mounted thereon. The slave devices 32 may be mounted on one side or both sides of the module. The module also includes a set of edge fingers 34 for coupling to the bus 28.
FIG. 3 is a top view of one of the modules 26 of FIG. 1. Module 26 has a set of slave devices 32A-32E mounted on it. Module leads 36 link the set of slave devices 32A-32E and thereby form a portion of the bus 28. Each slave device of FIG. 3 is enclosed in it""s own package 33A-33E.
The structure of FIGS. 1-3 represents state-of-the-art packaging for master-slave systems, such as memory subsystems, which are operated with a memory controller (master) and a set of random access memories (slaves). Each slave device of FIG. 2 is enclosed in its own package. Metal traces or module leads 36 are used between the packages.
Placing each slave device in its own package is relatively expensive. Furthermore, such an approach is relatively space-intensive. In addition, such an approach can result in substantive signal propagation delays between, for example, the first and last slave devices in a row of slave devices.
It would be highly desirable to improve the performance of semiconductor systems, such as master-slave systems in the form of memory systems. Such improvements could be exploited to support the increased information bandwidth of modern computers.
One embodiment of the invention defines an apparatus. The apparatus includes a first substrate having a set of semiconductor devices formed within it. The apparatus also includes a second substrate. A third substrate has a data conductor coupled between first and second connections to the second substrate. The data conductor is coupled to the set of semiconductor devices at respective connection points.
Another embodiment of the invention is a semiconductor system with an interconnect channel with an input end to receive a set of input signals and an output end to route a set of output signals. A set of semiconductor devices are formed in a substrate, with each semiconductor device of the set of semiconductor devices being designed for independent operability and being electrically isolated within the substrate from adjacent semiconductor devices of the set of semiconductor devices. Each semiconductor device includes a set of input nodes and a set of output nodes formed on the surface of the substrate. The interconnect channel is positioned on the input nodes and the output nodes of each semiconductor device of the set of semiconductor devices. The set of input signals from the input end of the interconnect channel is applied to each semiconductor device of the set of semiconductor devices to produce the output signals at the output end of the interconnect channel.
The method of the invention includes the step of forming a set of semiconductor devices in a wafer. Each semiconductor device of the set of semiconductor devices is designed for independent operability and is electrically isolated within the substrate from adjacent semiconductor devices of the set of semiconductor devices. The forming step also includes the step of forming within each semiconductor device, a set of input nodes and a set of output nodes on the surface of the substrate. Faulty semiconductor devices and operable semiconductor devices are then identified within the set of semiconductor devices. A set of operable semiconductor devices that are adjacent to one another on the wafer are subsequently grouped. An interconnect channel is then applied to the set of operable semiconductor devices so as to electrically link input nodes and output nodes of each semiconductor device within the set of operable semiconductor devices.
The interconnect channel may be a set of metal traces positioned over the set of memory devices. Alternately, the interconnect channel may be formed on an interconnect substrate, such as a thin-film substrate, flexible tape, or a printed circuit board. The set of memory devices and the interconnect channel may be positioned in a single package.
The invention improves performance in semiconductor systems, such as master-slave memory systems. The improved performance increases information bandwidth of computer and computer subsystems. The invention produces high density systems with reduced signal propagation times. The high density systems of the invention reduce packaging costs and improve thermal performance.